Polymorphism in System Verilog

Today we will get conceptual understanding of System Verilog polymorphism. In simple words Poly means different forms. In system verilog it means different behavior of the same task/function in extended classes.

As per inheritance rule each class can be extended by another class which is child class. All the parent class properties are extended to child class. Methods (function/tasks) which is declared in parent class also be present in child class. you just need to declare and define it.

Example:

module top;
class A;
task disp();
$display("Class A\n");
endtask
endclass

class B extends A;
task disp();
$display("Class B\n");
endtask
endclass

initial
begin
A a_h = new();
B b_h = new();
a_h.disp();
b_h.disp();
end
endmodule

Result:

Class A
Class B

As you see, using parent handle we get display from parent class and using child handle you get display from child class.
If you need get the access of child method using parent, you need to make use of special keyword virtual in parent method and assign child handle to parent as shown below. Both steps need to be done.

Example:

module top;
class A;
virtual task disp();
$display("Class A\n");
endtask
endclass

class B extends A;
task disp();
$display("Class B\n");
endtask
endclass

initial
begin
A a_h = new();
B b_h = new();
a_h = b_h;
a_h.disp();
b_h.disp();
end
endmodule

Result:

Class B
Class B

Both parent and child handle method call will point to child method only. No need to make child method as virtual, as parent is virtual already.

That is first part of polymorphism. Next blog I will share few more things about it. Please feel free to ask for any questions